1. Technical Field
The embodiments described herein relate to a reference voltage supply circuit in a semiconductor memory apparatus, and more particularly, to a circuit and a method for supplying a reference voltage to a semiconductor memory apparatus for testing the reference voltage.
2. Related Art
Conventional semiconductor integrated circuits use power sources, such as an external supply voltage VDD and a ground voltage VSS, from the outside of a chip, and internal voltages such as a reference voltage (Vref), a peripheral voltage (Vperi), a core voltage (Vcore), an elevated voltage (VPP) and a substrate bias voltage (VBB). To generate these internal voltages, the semiconductor memory apparatus includes various voltage generators.
The reference voltage (Vref) is often used for generating the core voltage (Vcore) and the elevated voltage (VPP). In a conventional semiconductor memory apparatus, it is often the case that a reference voltage level used for a core voltage generator is different from that used for an elevated voltage generator. Consequently, a reference voltage generator is often configured to generate a core reference voltage for the core voltage generator and an elevate reference voltage for the elevated voltage generator respectively.
Meanwhile, a conventional semiconductor memory apparatus receives a reference voltage for buffering data through a reference voltage pad in order to support a buffering operation of input data in a data input buffer. The semiconductor memory apparatus also receives a reference voltage for buffering command addresses through a reference voltage pad in order to support a buffering operation of commands and addresses in a command/address buffer.
As mentioned above, the data buffer reference voltage and the command/address buffer reference voltage are provided externally through the pads. However, a core reference voltage and an elevate reference voltage are internally generated as described above. Generally, the manufacture of a conventional semiconductor memory apparatus includes a wafer test and a package test. However, because the core reference voltage and the elevate reference voltage are not input through a pad, it is not possible to test the core reference voltage and the elevate reference voltage using conventional methods. Accordingly, it is not possible to test for failures in the core reference voltage and the elevate reference voltage after the completion of the package process, which degrades the efficiency of the package test. Consequently, the yield for conventional semiconductor apparatus is reduced because of the limitation on the package test, which also leads to increases in processing time and cost.